Pipelining – An overlapped parallelism
vTo
achieve pipelining one must subdivide the input into a sequence of subtask,
each of that executed concurrently with other stages in the pipeline
Principles
of Linear Pipelining
qAssembly
lines used in automated industries to increase productivity
qAll
assembly lines in a pipelined processors must have same processing speed
qElse
congestion problem may occur.
qThe
precedence relation of a set of subtasks says that one state Tj
cannot start until Ti finishes.
qLinear
Pipelining process.
Clock Period:
-time delay
Tk=k+(n-1) denotes the output /result at
each clock cycles
Speed Up:
Sk=T1/Tk=n.k/k+(n-1)
Classification
of pipelined processors
Handler
has proposed the following 6 schemas:
ÒArithmetic
pipelining
ÒInstruction
pipelining
ÒProcessor
pipelining
ÒUnifunction
vs multifunction pipelines
ÒStatic
vs dynamic pipelines
ÒScalar
vs vector pipelines
GENERAL
PIPELINES AND RESERVATION TABLES
ÒLinear
Pipeline – depends on the output to process the next instruction
ÒPipelines
with feedback may have a non linear data flow
ÒGeneral
Pipelines with feedback connections and feed forward
ÒNeed
to use the reservation table
ÒForward
connection –> j>=i+2
Feedforward
connection j<=i
Interleaved
memory organisation
ÒMemory
bandwidth – avg no of words accessed per second
ÒFactors
affecting the bandwidth are:
Processor architecture
Memory configuration
Memory module characteristics(Clock cycle,
memory org)
Eg:
four pipeline vector processors
ÒS-
access memory organization
ÒC-
access memory organization
ÒC/S
access memory organization
S- access
memory organization
ÒIt
uses simply low order interleaving and applies (n-m) bits of the address to all
M=2 memory modules in one access
ÒAll
the modules gets accessed simultaneously
ÒHere,
high order bits selects modules
ÒWords
from modules are latched at the same time
ÒLower
order bits selects word from latches
ÒThis
is done through MUX with higher speed
C-access
memory organisation
ÒIt
allows m memory words to be accessed
concurrently
ÒMore
than one bank can be accessed so that it increases the bank utilisation
and reducing the bank cost.
ÒThis
is C-access m/y organisation
C/S access
memory organisation
ÒN
access busses with m interleaved memory modules
Ò
n busess operates in parallel to allow S access
ÒCombination
of both S access and C access
